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1. INTRODUCTION
ST
ST7549T
68 x 102 Dot Matrix LCD Controller/Driver
The ST7549T is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 102 segment and 67 common with 1 ICON driver circuits. This chip is connected directly to a microprocessor, accepts 3-line or 4-line serial peripheral interface (SPI), I2C interface or 8-bit parallel interface, display data can stores in an on-chip display data RAM of 68 x 102 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Single-chip LCD controller & driver Driver Output Circuits 102 segment / 67 common+1 ICON common (1/68 duty) 102 segment / 32 common+1 ICON common (1/33 duty) 102 segment / 16 common+1 ICON common (1/17 duty) (1/33 duty and 1/17 duty are under partial screen mode) On-chip Display Data Ram n n n n n n Capacity: 68X102=6,936 bits 8-bit parallel bi-directional interface with n n Microprocessor Interface 6800-series or 8080-series 4-line SPI (serial peripheral interface) available (only write operation) 3-line SPI (serial peripheral interface) available I2 C (Inter-Integrated Circuit) Interface n n n n voltage supply is possible) Generation of intermediate LCD bias voltages Oscillator without external components (external clock also possible) Voltage Booster (X2,X3,X4,X5) Voltage Regulator (temperature gradient -0.11%/C) Voltage Follower On-chip electronic contrast control function (255 steps) External RESB (reset) pin Supply voltage range n n n VDD1 -VSS : 1.7 to 3.3V VDD2 VOUT -VSS : 2.4 to 3.3V -VSS : 13.5V (Max.)
On-chip Low Power Analog Circuit Generation of LCD supply voltage (externally VOUT
Temperature range: -30 to +85 degree Package Type: COG
6800, 8080, ST7549T-G2 4-Line, 3-Line interface (without I2C interface) ST7549Ti-G2 I2C interface
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3. ST7549T-G2 Pad Arrangement (COG)
Chip Size: 8,200 um x 1020 um Bump Pitch: PAD NO 1 ~ 11 , 12 ~ 147 , 207 ~ 230 : 55 um ; PAD NO 148 ~ 216 : max : 175 um , min : 72 um Bump Size: PAD NO 188 ~ 193 : 45 (x)um x 60 (y) um ; ; ; ; PAD NO 11 ~ 12 : 56 um ;
PAD NO 148 ~ 187 , 194 ~ 206 : 55 (x) um x 60 (y) um PAD NO 124 ~ 137 , 217 ~ 230: 96 (x) um x 37 (y) um PAD NO 1 ~ 123 , 138 ~ 147 , 207 ~ 216 : Bump Height: 17 um Chip Thickness: 480 um
37 (x) um x 96 (y) um
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Pad Center Coordinates(68 Duty)
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN Name COM[43] COM[42] COM[41] COM[40] COM[39] COM[38] COM[37] COM[36] COM[35] COM[34] COM[33] SEG[0] SEG[1] SEG[2] SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] X 3677 3622 3567 3512 3457 3402 3347 3292 3237 3182 3127 3071 3016 2961 2906 2851 2796 2741 2686 2631 2576 2521 2466 2411 2356 2301 2246 2191 2136 2081 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 PAD NO. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PIN Name SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] X 2026 1971 1916 1861 1806 1751 1696 1641 1586 1531 1476 1421 1366 1311 1256 1201 1146 1091 1036 981 926 871 816 761 706 651 596 541 486 431 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371
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PAD NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PIN Name SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] X 376 321 266 211 156 101 46 -9 -64 -119 -174 -229 -284 -339 -394 -449 -504 -559 -614 -669 -724 -779 -834 -889 -944 -999 -1054 -1109 -1164 -1219 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 PAD NO. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name SEG[79] SEG[80] SEG[81] SEG[82] SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] COMS COM[0] COM[1] COM[2] COM[3] COM[4] COM[5] X -1274 -1329 -1384 -1439 -1494 -1549 -1604 -1659 -1714 -1769 -1824 -1879 -1934 -1989 -2044 -2099 -2154 -2209 -2264 -2319 -2374 -2429 -2484 -2540 -2595 -2650 -2705 -2760 -2815 -2870 Y 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371 371
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PAD NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 PIN Name COM[6] COM[7] COM[8] COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[17] COM[18] COM[19] COM[20] COM[21] COM[22] COM[23] COM[24] COM[25] COM[26] COM[27] COM[28] COM[29] COM[30] COM[31] COM[32] T6 T7 VDD1 X -2925 -2980 -3035 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3981 -3678 -3623 -3568 -3513 -3458 -3403 -3348 -3293 -3238 -3183 -2194 -2075 -2002 Y 371 371 371 352 297 242 187 132 77 22 -33 -88 -143 -198 -253 -308 -363 -371 -371 -371 -371 -371 -371 -371 -371 -371 -371 -389 -389 -389 PAD NO. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 PIN Name VDD1 VDD1 VDD1 PS0 PS1 PS2 BR VSS T8 T9 CP T10 T11 VDD2 VDD2 VDD2 VDD2 RESB CSB /WR /RD A0 VDD1 D7 D6 D5 D4 D3 D2 D1 X -1929 -1856 -1783 -1710 -1591 -1518 -1399 -1326 -1253 -1134 -1061 -942 -869 -766 -693 -620 -547 -410 -291 -218 -99 -26 77 150 269 342 461 534 653 726 Y -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389
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PAD NO. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 PIN Name D0 OSC VSS VSS VSS VSS VRS T0 T1 T2 T3 T4 T5 VSS VSS VSS VSS VOUTOUT VOUTOUT VOUTIN VOUTIN V0 V1 V2 V3 V4 COMS COM[66] COM[65] COM[64] X 845 918 1021 1094 1167 1240 1313 1385 1534 1609 1784 1859 2034 2108 2181 2254 2327 2415 2488 2561 2634 2793 2883 2956 3029 3102 3183 3238 3293 3348 Y -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -389 -371 -371 -371 -371 PAD NO. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 PIN Name COM[63] COM[62] COM[61] COM[60] COM[59] COM[58] COM[57] COM[56] COM[55] COM[54] COM[53] COM[52] COM[51] COM[50] COM[49] COM[48] COM[47] COM[46] COM[45] COM[44] X 3403 3458 3513 3568 3623 3678 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 3981 Y -371 -371 -371 -371 -371 -371 -363 -308 -253 -198 -143 -88 -33 22 77 132 187 242 297 352
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4. BLOCK DIAGRAM
Fig.1 block diagram
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5. PINNING DESCRIPTIONS
LCD Driver outputs Pin Name I/O Description LCD segment driver outputs. This display data and the M signal control the output voltage of segment driver. Segment drover output voltage Display data M (Internal) Normal display Reverse display SEG0 to SEG101 No. of Pins
O
H
H
V0 VSS V2 V3 VSS
V2 V3 V0 VSS VSS
102
H L L H L L Power save mode
LCD column driver outputs This internal scanning data and M signal control the output voltage of common driver. COM0 to COM66 Common drover output voltage Normal display Reverse display VSS V0 V1 V4 VSS
O
Display data
M(Internal)
H H H L L H L L Power save mode
67
COMS
O
Common output for the icons The output signals of two pins are same. When not used, this pin should be left open.
2
MICROPROCESSOR INTERFACE Pin Name I/O Description Microprocessor interface select input pin PS0 "L" "L" "L" "L" "H" PS1 "L" "L" "H" "H" "H" PS2 "L" "H" "L" "H" "H" State 4 Pin-SPI MPU interface 3 Pin-SPI MPU interface 8080-series parallel MPU interface 6800-series parallel MPU interface 2 I C interface No. of Pins
PS[2:0]
I
3
CSB
I
RESB
I
A0
I
Chip select input pins Data/instruction I/O is enabled only when CSB is " L ". When chip select is non-active, DB0 to DB7 is high impedance. 2 There is no CSB pin in I C interface, so this pin can fix to " H" Reset input pin When RESB is " L ", initialization is executed. It determines whether the data bits are data or a command. A0=" H ": Indicates that D0 to D7 are display data. A0=" L ": Indicates that D0 to D7 are control data. 2 There is no A0 pin in three line or I C interface, so this pin can fix to " H"
1
1
1
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Pin Name I/O Description Read/Write execution control pin (PS[0:1]=[L:H]) PS2 MPU type /WR(R/W) Description Read/Write control input pin H 6800-series R/W R/W=" H ": read R/W=" L": write Write enable clock input pin The data on D0 to D7 are latched L 8080-series /WR at the rising edge of the /WR signal When in the serial interface must fix to " H" Read/Write execution control pin (PS[0:1]=[L:H]) PS2 MPU Type /RD (E) Description Read/Write control input pin R/W=" H ": When E is " H ", D0 to D7 are in an output status. H 6800-series E R/W=" L ": The data on D0 to D7 are latched at the falling edge of the E signal. Read enable clock input pin L 8080-series /RD When /RD is " L ", D0 to D7 are in an output status. When in the serial interface must fix to " H" When using 8-bit parallel interface : 6800 . 8080 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When chip select is not active, D0 to D7 is high impedance. When using serial interface: 4-LINE D0: serial input clock (SCLK) D1,D2, D3 : serial input data (SDA), must be connected together D4, D5, D6, D7 : must fix to " H" When chip select is not active, D0 to D7 is high impedance. When using serial interface: 3-LINE D0 : serial input clock (SCLK) D1 : serial input data (SDA_IN) D2, D3 : serial data output for read ID function(SDA_OUT) D4 : ID1 ,When connect to VSS, ID1=0;connect to VDD,ID1=1 D5 : ID2 ,When connect to VSS, ID2=0;connect to VDD,ID2=1 D6 : ID3 ,When connect to VSS, ID3=0;connect to VDD,ID3=1 D7 : ID4 ,When connect to VSS, ID4=0;connect to VDD,ID4=1 Suggest D1~D3 be connected together; Suggest D4~D7(ID1~ID4) be connected to VDD if not used When chip select is not active, D0 to D7 is high impedance. No. of Pins
/WR(R/W)
I
1
/RD (E)
I
1
D7 to D4 D1 to D3 (SDA) D0(SCLK)
I/O
8
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Pin Name I/O
2
Description When using I C interface D0: serial clock input (SCLK) D1: serial input data (SDA_IN) 2 D2, D3: (SDA_OUT) serial data acknowledge for the I C interface. By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully 2 I C interface compatible. Having the acknowledge output separated from the serial data line is advantageous in chip on glass (COG) applications. In COG application where the track resistance from the SDA_OUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. It is possible the during the acknowledge cycle the ST7549T will not be able to create a valid logic 0 level. By splitting the SDA_IN input from the SDA_OUT output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDA_OUT pad to the system SDA line to guarantee a valid low level. D1,D2,D3 must be connected together (SDA) D4, D5: must fix to " H" D6, D7: Is slave address (SA) bit1, 0, must fix to "H" or "L" Chip select input pins "CSB" not used must fix to "H"
No. of Pins
D7 to D6 (SA) D5 to D4(X) D3 to D2 (SDA_OUT) D1 (SDA_IN) D0 (SCLK)
LCD DRIVER SUPPLY Pin Name I/O Description When the on-chip oscillator is used, this input must be connected to VDD. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting the OSC pin to VSS the display is not clocked and may be left in a DC state. To avoid this, the chip should always be put into Power Down Mode before stopping the clock. Description Ground. VSS Power Supply Digital Supply voltage:1.7V~3.3V The 2 supply rails VDD1 and VDD2 could be connected together. If Digital Option pin is high, must be this level Analog Supply voltage:2.4V~3.3V The 2 supply rails VDD1 and VDD2 could be connected together. 9 No. of Pins
OSC
I
1
Power Supply Pins Pin Name I/O No. of Pins
VDD1
Power Supply
5
VDD2
Power Supply
4
VOUTIN
Power Supply
VOUTOUT
Power Supply
If the internal voltage generator is used, the VOUTIN & VOUTOUT must be connected together. An external supply voltage can be supplied using the VOUTIN pad. This pad is for external multiple voltage input. In this case, VOUTOUT has to be left open, If the internal voltage generator is used, the VOUTIN & VOUTOUT must be connected together and series one capacitor to VSS If an external supply is used this pin must be left open.
2
2
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Pin Name I/O Power Supply Description This is a multi-level power supply for the liquid crystal. VOUTIN V0 V1V2V3V4VSS No. of Pins
V0, V1, V2, V3, V4
5
Monitor Voltage Regulator level, must be left open. VRS Power Supply 1
Configuration Pins Pin Name CP BR Test Pin Pin Name T0~T11 I/O T Description T0~T7 must floating T8.T9.T10 must connect to VDD T11 must connect to VSS No. of Pins 10 I/O I I Description Set Booster stages. (VSS=4X;VDD=5X) CP pin set the default value of booster stages after reset , and booster stage can be changed by software instruction Set LCD bias ratio. (VSS=1/7;VDD=1/9) BR pin set the default value of bias ratio after reset , and bias ratio can be changed by software instruction No. of Pins 1 1
ST7549T I/O PIN ITO Resister Limitation PIN Name PS[2:0],OSC,CP,BR,T8~T11 T0~T7,VRS, V1 , V2 , V3 , V4 VDD1 , VDD2 , VSS , VOUTIN , VOUTOUT ; D1~D3 (if I2C mode) V0 A0,/WR,/RD,CSB, D0 ...D7 RESB ITO Resister No Limitation Floating <100 <500 <1K <10K
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6. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE Chip Select Input There is CSB pin for chip selection. The ST7549T can interface with an MPU when CSB is "L". When CSB is "H", these pins are set to any other combination, A0, /RD(E), and /WR(R/W) inputs are disabled and D0 to D7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface ST7549T has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial interface is determined by PS [0:2] pin as shown in table 1. Table 1. Parallel/Serial Interface Mode PS0 "L" "L" "L" "L" "H" PS1 "L" "L" "H" "H" "H" PS2 "L" "H" "L" "H" "H" CSB CSB CSB CSB CSB "*" A0 A0 "*" A0 A0 "*" State 4 Pin-SPI MPU interface 3 Pin-SPI MPU interface 8080-series parallel MPU interface 6800-series parallel MPU interface 2 I C interface
Parallel Interface The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS2 as shown in table 2. The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in table 3. Table 2. Microprocessor Selection for Parallel Interface PS2 CSB A0 /RD (E) /WR (R/W) DB0 to DB7 MPU bus H CSB A0 E R/W DB0 to DB7 6800-series L CSB A0 /RD /WR DB0 to DB7 8080-series Table 3. Parallel Data Transfer 8080-series Description /RD /WR (E) (R/W) L H Display data read out H L Display data write L H Register status read H L Writes to internal register (instruction)
PS0 L L
PS1 H H
Common A0 H H L L
6800-series E R/W (/RD) (/WR) H H H L H H H L
NOTE: When /RD (E) pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, /WR(R/W) as in case of 6800-series mode. Serial Interface Serial Mode PS0 PS1 PS2 CSB A0 4-line SPI interface L L L CSB Used L L H CSB Not Used 3-line SPI interface Fix to "H" H H H Not Used Not Used 2 I C interface Fix to "H" Fix to "H" PS0=" L ", PS1=" L ", PS2=" L ": 4-line SPI interface When the ST7549T is active (CSB="L"), serial data (D1) and serial clock (D0) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be controlled either via software or the Register Select (A0) Pin, based on the setting of PS[2:0]. When the A0 pin is used , data is display data when A0 is high, and command data when A0 is low. When A0 is not used , the LCD Driver will receive command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data direction command to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are sending, the following messages will be data rather than command. Serial data can be read on
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the rising edge of serial clock going into D0 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string are handled as command data.
/CSB SDA SCLK A0
Fig. 2 4-line SPI Timing
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6
PS0=" L ", PS1=" L ", PS2=" H ": 3-line SPI interface
/CSB SDA SCLK
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0
Fig. 3-1 3-line SPI Timing
"D/C": the same as A0
Figure 1-2 shows the timing of reading on one bit of B1....B4
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To access Driver TxData-mode a Self Test command is needed to write to driver. The first bit (A0) is low to indicate next 8-bits are for command. The data is read to the driver on the rising edge of SCLK. After last command bit (bit 0) is read SDA-out becomes active (Low impendence) and MCU is able to read data from driver. The data is read to 8-bit register in MCU so that the bit which was the object of reading is MSB (D7). The same bit value is the written again to the register 3 times in a row by next 3 rising edges of SCLK. These first 4 bits are MSB. The 4 LSB is written to the register as the complement of 4 MSB by 4 next rising edges of SCLK. The complement function is done by the driver. This function allows to check if the written data is valid. After written all 8 bits to the register the Auto Return-block in driver release automatically driver back to the MCU TxData-mode, MCU Txdata line changes from high-z to active low in the falling edge of 8th SCLK pulse. CSB must be set high and low again before A0 writing can continue. SDA-out and SDA-in line can be short circuited in normal working conditions. Bit No. Status D7(MSB) 0 or 1 D6 D5 D4 Bits have same status as MSB D3 D2 D1 D0(LSB) Bits are complement of 4 MSB (D7~D4)
For example, if D7 (MSB) has status "0" first 4 bits (D7~D4) represent the status of D7 ("0") and next four bits (D3~D0) have status "1" because they represent complement data of D7~D4 (see the figure below) It is recommended to use below 1 MHz SCLK speed for Driver Tx mode (both self test command writing and reading of status). This guarantees that D7 and D6 status bits are also valid.
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PS0= "H" , PS1= "H" , PS2= "H" : I C Interface 2 2 The I C interface receives and executes the commands sent via the I C Interface. It also receives RAM data and sends it to the RAM. 2 The I C Interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.4. START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.5. SYSTEM CONFIGURATION The system configuration is illustrated in Fig.6. * Transmitter: the device, which sends the data to the bus * Receiver: the device, which receives the data from the bus * Master: the device, which initiates a transfer, generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices. ACKNOWLEDGE Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a 2 STOP condition. Acknowledgement on the I C Interface is illustrated in Fig.7.
2
SDA SCL
data line stable; data valid change of data allowed
Fig .4 Bit transfer
Fig .5 Definition of START and STOP conditions
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MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER (1) 0111100 SLAVE RECEIVER (2) 0111101 SLAVE RECEIVER (3) 0111110 SLAVE RECEIVER (4) 0111111
SDA SCL
Fig .6 System configuration
DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER 1 2
not acknowledge acknowledge 8 9 clock pulse for acknowledge ment
2
S
START condition
Fig .7 Acknowledgement on the I C Interface
I C Interface protocol The ST7549T supports command, data write addressed slaves on the bus. 2 Before any data is transmitted on the I C Interface, the device, which should respond, is addressed first. Four 7-bit slave addresses (0111100,0111101, 0111110 and 0111111) are reserved for the ST7549T. The least significant bit of the slave address is set by connecting the input SA0 and SA1 to either logic 0 (or logic 1 (VDD1). 2 The I C Interface protocol is illustrated in Fig.8. The sequence is initiated with a START condition (S) from the I C Interface master, which is followed by the slave address. 2 All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I C Interface transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and A0, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the A0 bit defines whether the data byte is interpreted as a command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the A0 bit setting; either a series of display data bytes or command data bytes may follow. If the A0 bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended ST7549T device. If the A0 bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received 2 commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I C INTERFACE-bus master issues a STOP condition (P).If the R/W bit is set to logic 1 the chip will output data immediately after the slave address if the A0 bit, which was sent during the last write access, is set to logic 0. If no acknowledge is generated by the master after a byte, the driver stops transferring data to the master.
2
2
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Write mode
acknowledgement from ST7549
S A 1 S A 0
acknowledgement from ST7549
acknowledgement from ST7549
acknowledgement from ST7549
acknowledgement from ST7549
S01111 slave address
0 A1
R/W
A 0
control byte
A
data byte
A0
A 0
control byte
A
data byte
AP
2n>=0bytes command word Co Co
1 byte
n>=0bytes MSB.......................LSB
01111
S A 1
S A 0
R / W
Co
A 0
000000A control byte
slave address
Co
0 1
Fig .8 I C Interface protocol Last control byte to be sent. Only a stream of data bytes is allowed to follow. This stream may only be terminated by s STOP or RE-START condition. Another control byte will follow the data byte unless a STOP or RE-START condition is received.
2
Data Transfer The ST7549T uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 9. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 10. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data.
MPU signal A0 /WR D0 to D7 Internal signals /WR BUS HOLDER COLUMN ADDRESS N D(N) N D(N+1) N+1 D(N+2) N+2 D(N+3) N+3 N D(N) D(N+1) D(N+2) D(N+3)
Fig.9 Write Timing
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MPU signal A0 /W R /RD D0 to D7 Internal signals /W R /RD BUS HOLDER COLUMN ADDRESS N N D(N) D(N) D(N+1) D(N+1) D(N+2) D(N+2) N Dummy D(N) D(N+1)
Fig.10 Read Timing
DISPLAY DATA RAM (DDRAM) The ST7549T contains a 68X102 bit static RAM that stores the display data. The display data RAM store the dot data for the LCD. It has a 68(8 pageX8 bit +1 pageX3 bit +1 pageX1 bit) X 102 . There is a direct correspondence between X-address and column output number. It is 68-row by 102-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines (0~63 COM) and 8th page with three line (D0 ~D2)(64~ 66 COM) and 9th page with a single line (D0 only)(67 row--COMS (ICON). Data is read from or written to the 8 lines of each page directly through D0 to D7. The display data of D0 to D7 from the microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. Page Address Circuit This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 9 is a special RAM area for the icons and display data D0 is only valid. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 10. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 102-bit RAM data to the display data latch circuit. When icon is selected by setting icon page address, display data of icons are not scrolled because the MPU cannot access Line Address of icons.
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Column Address Circuit Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in figure11. The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Register MX and MY selection instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing MX select instruction. Refer to the following figure 12. SEG Output SEG Output MX SEG0 SEG101 "0" seg0 a Segment Address a seg101 "1" seg101 Segment Address seg0 Com Output SEG Output MY Com0 Com66 Coms "0" com0 a Common Address a com66 Coms "1" com66 Common Address com0 Coms
Duty
MY 0 1
Common output pins Com [0:66] Com [0:66] Com [66:0] Coms Coms Coms
1/68
ADDRESSING Data is downloaded in bytes into the RAM matrix of ST7549T as indicated in Figs.11, 12, 13, 14. The display RAM has a matrix of 68 by 102 bits. The address pointer addresses the columns. The address ranges are: X 0 to 101 (1100101), Y 0 to 9 (1001) .Addresses outside these ranges are not allowed. In horizontal addressing mode the X address increments after each byte (see Fig.14). After the last X address (X = 101) X wraps around to 0 and Y increments to address the next row. After the very last address (X = 101, Y = 9) the address pointers wrap around to address (X = 0, Y =0)
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Data structure LSB
D0
D7
MSB LSB MSB 1 bit 0 X-address Fig.11 RAM format, addressing , if DO=0 101
0 1 2 3 4 5 6 7 8 9
D7
MSB
D0
LSB MSB LSB 1 bit 0 X-address
Fig.12 RAM format, addressing, if DO=1
0 1 2 3 4 5 6 7 8 9 101
012 102103104 204205206 306307308 408409410 510511512 612613614 714715716 816817818 0 X-address
917 101
0 1 2 3 4 5 6 7 8 9
Fig.14 sequence of writing data bytes into RAM with horizontal addressing
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Y-address
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Y-address
Y-address
ST7549T
Page Address Data D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D0 00 01 02 03 04 05 06 07 08 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H DO 5D 5E 5F 60 61 62 63 64 65 0 Column address When the common output is normal COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 ICON (COMS) Regardless of the display start line address, 1/68duty => 67th line
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1 1
0 0
0 0
0 1
Page 8 Page 9
S100
S101
Fig.16 Display Data RAM Map (68 COM)
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LCD Out
S93
S94
S95
S96
S97
S98
S99
S0
S1
S2
S3
S4
S5
S6
S7
S8
DO
5D
5E
5F
65
64
63
62
61
60
08
07
06
05
04
03
02
01
00
1
MX
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ST7549T
LCD DRIVER CIRCUIT 68-channel common drivers and 102-channel segment drivers configure this driver circuit. This LCD panel driver voltage depends on the combination of display data and M signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
M
VDD VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0
COM0
COM1
COM2
SEG0
SEG1
SEG 0 1 2 3 4
COM0 to SEG0
COM0 to SEG1
Fig.19 Typical LCD driver waveforms
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Partial Display on LCD The ST7549T realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages.
Figure 20.Reference Example for Partial Display
Figure 21.Partial Display (Partial Display Duty=16,initial COM0=0)
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Figure 22.Moving Display (Partial Display Duty=16,Initial COM0=8)
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7. RESET CIRCUIT
Setting RESB to "L" or Reset instruction can initialize internal function. When RESB becomes "L", following procedure is occurred. Page address: 0 Column address: 0 Display control: Display blank COM Scan Direction MY: 0 SEG Select Direction MX: 0 DO=0 FR[2:0]=100 Oscillator: OFF N-line inversion register: 0 (disable) Power down mode (PD = 1) Normal instruction set (H[1:0] = 00) Display blank (E = D = 0) Address counter X [6:0] = 0, Y [3:0] = 0 Bias system (BS [2:0] = BR setting) V0 is equal to 0; the HV generator is switched off (V OP [6:0] = 0) After power-on, RAM data are undefined While RESB is "L" or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB0. After DB0 becomes "L", any instruction can be accepted. RESB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESB is essential before used.
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8. INSTRUCTION TABLE
INSTRUCTION A0
WR (R/W)
D7 0 0 0 PD D7 D7
D6 0 0 0 0 D6 D6
D5 0 0 1 0 D5 D5
COMMAND BYTE D4 D3 D2 0 0 MX D D4 D4 0 0 MY E D3 D3 0 0 PD MX D2 D2
D1 0 0 H1 MY D1 D1
D0 0 1 H0 DO D0 D0
DESCRIPTION No operation Do not use Power-down; entry mode; Extended instruction control Read status byte Read data to RAM Write data to RAM
H independent instruction NOP 0 0 Reserved 0 0 Function set Read status byte Read data Write data 0 0 1 1 0 1 1 0
WR (R/W)
INSTRUCTION H[1:0]=[0:0] Reserved Set VOP range END Read/modify/write Display control Reserved Set Y address of RAM Set X address of RAM H[1:0]=[0:1] Reserved Display configuration Bias system Set Start line Set VOP
A0 0 0 0 0 0 0 0 0 0 0 0 0 0
D7 0 0 0 0 0 0 0 1 0 0 0 0 1
D6 0 0 0 0 0 0 1 X6 0 0 0 1 VOP6
D5 0 0 0 0 0 0 0 X5 0 0 0 S5 VOP5
COMMAND BYTE D4 D3 D2 0 0 0 0 0 1 0 X4 0 0 1 S4 VOP4 0 0 0 0 1 0 Y3 X3 0 1 0 S3 VOP3 0 1 1 1 D 0 Y2 X2 0 DO BS2 S2 VOP2
D1 1 0 1 1 0 X Y1 X1 1 X BS1 S1 VOP1
D0 X PRS 0 1 E X Y0 X0 X X BS0 S0 VOP0
DESCRIPTION Do not use VOP range L/H select Release read/modify/write RAM address at R:+0 , W:+1 Sets display configuration Do not use Sets Y address of RAM 0Y9 Sets X address of RAM 0X101 Do not use Top/bottom row mode set data order Sets bias system (BSx) Specify the initial display line to realize vertical scrolling Write VOP to register
0 0 0 0 0 0 0 0 0 0 0 0 0
INSTRUCTION
A0
WR (R/W)
D7 0 0 0 0 0 0 0 1 1
D6 0 0 0 0 0 0 1 0 X
D5 0 0 0 0 0 0 0 0 X
COMMAND BYTE D4 D3 D2 0 0 0 1 0 0 NL4 1 X 0 0 1 0 0 1 NL3 BE1 X 0 1 0 DP2 0 FR2 NL2 BE0 X
D1 1 0 0 DP1 1 FR1 NL1 PC1 X
D0 X PS WS
DESCRIPTION
H[1:0]=[1:0] Reserved 0 Partial screen mode 0 Partial screen size 0 Display part 0 H[1:0]=[1:1] RESET Display control N line inversion Booster Efficiency &Booster Stage Reserved 0 0 0 0 0
0 0 0 0 0 0 0 0 0
Do not use Partial screen enable Set partial screen size Set display part for partial DP0 screen mode 1 FR0 NL0 PC0 X Software reset Frame rate control Sets N line inversion Booster Efficiency Set Do not use
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Only used in 3-line to read ID
INSTRUCTION H[1:0]=[1:1] Self test/identification Data read A0 D7 D6 D5 COMMAND BYTE D4 D3 D2 1 1 1 1 1 1 1 1 0 0 1 1 D1 1 1 0 0 D0 0 1 0 1 DESCRIPTION Identification:ID1 Identification:ID2 Identification:ID3 Identification:ID4
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 SDA_IN and SDA_OUT must be connected together.
9. INSTRUCTION DESCRIPTION
Function Set
A0 0 Flag MX
WR(R/W)
0
D7 0
D6 0
D5 1
D4 MX
D3 MY
D2 PD
D1 H1
D0 H0
MY
PD
H0.H1
Description SEG bi-direction selection MX=0:normal direction (SEG0->SEG101) MX=1:reverse direction (SEG101->SEG0) COM bi-direction selection MY=0:normal direction (COM0->COM66) MY=1:reverse direction (COM66->COM0) All LCD outputs at VSS (display off), bias generator and VOP generator off, VOUT can be disconnected, oscillator off (external clock possible), RAM contents not cleared; RAM data can be written. PD=0:chip is active PD=1:chip is in power down mode H0.H1 are used to select different instruction block Follow the instruction table
Read status byte
Indicates the internal status of the ST7549T D7 D6 D5 A0 WR(R/W) 0 1 PD 0 0 Flag PD D4 D D3 E D2 MX D1 MY D0 DO
D,E
DO
Description PD=0:chip is active PD=1:chip is in power down mode D E The bits D and E select the display mode. 0 0 Display blank 0 1 All display segments on 1 0 Normal mode 1 1 Inverse video mode DO=0:LSB is on top DO=1:MSB is on top See page 20
Read data 8-bit data of Display Data from the RAM location specified by the column address and page address can be read to the microprocessor. A0 D7 D6 D5 D4 D3 D2 D1 D0 WR(R/W) 1 1 Read data
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Write data 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 1
WR(R/W)
D7
D6
D5
0
D4 D3 Write data
D2
D1
D0
H[1:0]=[0:0] Set VOP range VOP range L/H select D7 D6 A0 WR(R/W) 0 0 0 0 PRS=0: VOP programming range LOW PRS=1: VOP programming range HIGH Display Control This bits D and E selects the display mode. D7 D6 A0 WR(R/W) 0 0 0 0 Flag
D5 0
D4 0
D3 0
D2 1
D1 0
D0 PRS
D5 0
D4 0
D3 1
D2 D
D1 0
D0 E
D,E
Description D E The bits D and E select the display mode. 0 0 Display blank 1 0 Normal display 0 1 All display segments on 1 1 Inverse video mode
Set Y address of RAM Y [3:0] defines the Y address vector address of the display RAM. A0 D7 D6 D5 D4 D3 WR(R/W) 0 0 0 1 0 0 Y3 Y3 0 0 0 0 0 0 0 0 1 1 Y2 0 0 0 0 1 1 1 1 0 0 Y1 0 0 1 1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 0 1 0 1 CONTENT Page0 (display RAM) Page1 (display RAM) Page2 (display RAM) Page3 (display RAM) Page4 (display RAM) Page5 (display RAM) Page6 (display RAM) Page7 (display RAM) Page8 (display RAM) Page9 (display RAM)
D2 Y2
D1 Y1
D0 Y0
ALLOWED X-RANGE 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101 0 to 101
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Set X address of RAM The X address points to the columns. The range of X is 0...101. A0 D7 D6 D5 D4 WR(R/W) 0 0 1 X6 X5 X4 X6 0 0 0 0 : 1 1 1 1 X5 0 0 0 0 : 1 1 1 1 X4 0 0 0 0 : 0 0 0 0 X3 0 0 0 0 : 0 0 0 0 X2 0 0 0 0 : 0 0 1 1 X1 0 0 1 1 : 1 1 0 0 D3 X3 X0 0 1 0 1 : 0 1 0 1 D2 X2 D1 X1 D0 X0
Column address 0 1 2 3 : 98 99 100 101
END This command releases the read/modify/write mode, and returns the column and row address to the address it was at when the mode was entered. A0 D7 D6 D5 D4 D3 D2 D1 D0 WR(R/W) 0 0 0 0 0 0 0 1 1 0 Read/modify/write This command is used paired with the"END"command. Once this command has been input, the display data read command does not change the column and row address, but only the display data write command increments (+1) the address depend on V register setting. This mode is maintained until the END command is input. When the END command is input, the address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. A0 D7 D6 D5 D4 D3 D2 D1 D0 WR(R/W) 0 0 0 0 0 0 0 1 1 1 * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
Page address set Column address set Read - modify - Write Dummy Read Data read Data write NO Changes YES END
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H[1:0]=[0:1]
Display configuration Top/bottom row mode set data order A0 D7 D6 WR(R/W) 0 0 0 0 Flag DO Description DO=0:LSB is on top DO=1:MSB is on top See page 20 D5 0 D4 0 D3 1 D2 DO D1 X D0 X
System Bias Select LCD bias ratio of the voltage required for driving the LCD. D7 D6 D5 D4 D3 A0 WR(R/W) 0 0 0 0 0 1 0 BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 Bias 11 10 9 8 7 6 5 4
D2 BS2
D1 BS1
D0 BS0
Recommend Duty 1:100 1:81 1:65/1:68 1:49 1/40:1/36 1/24 1:18/1:16 1:10/1:9/1:8
LCD bias voltage Symbol V0 (VOP) V1 V2
Bias voltage for 1/9 bias V0 (VOP) 8/9 X V0 7/9 X V0
Symbol V3 V4 VSS
Bias voltage for 1/9 bias 2/9 X V0 1/9 X V0 VSS
Set start line Sets the line address of display RAM to determine the initial display line instruction. The RAM display data is displayed at the top of row (COM0) of LCD panel. A0 0 S5 0 0 0 0 : 1 1 1 1
WR(R/W)
0 S4 0 0 0 0 : 1 1 1 1
D7 0 S3 0 0 0 0 : 1 1 1 1
D6 1 S2 0 0 0 0 : 1 1 1 1
D5 S5 S1 0 0 1 1 : 0 0 1 1
D4 S4
D3 S3 S0 0 1 0 1 : 0 1 0 1
D2 S2
D1 S1 Line address 0 1 2 3 : 61 62 62 63
D0 S0
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Set VOP value: A0 D7 D6 D5 WR(R/W) 0 0 1 VOP6 VOP5 The operation voltage VOP can be set by software. D4 VOP4 D3 VOP3 D2 VOP2 D1 VOP1 D0 VOP0
V0=( a + VOPxb )
(1)
The parameters are explained in table 4.The maximum voltage that can be generated is depending on the VDD1 voltage and the display load current. Two overlapping V0 ranges are selectable via the command "Booster control". For the LOW (PS=0) range a=a1 and for the HIGH (PRS=1) range a=a2 with steps equal to "b" in both ranges. Note that the charge pump is turned off if VOP [6;0] and the bit PRS are all set to zero
Table 4 Typical values for parameter for the HV-Generator programming SYMBOL VALUE UNIT a1 2.94(PRS=0) V a2 6.75(PRS=1) V b 0.03 V
VL2
b
Charge pump off
a2 a1+b 01 02 03 04 05 06 ..... 7D 7E 7F 00 01 02 03 04 05 06 ..... 7D 7E 7F
00
LOW(PRS=0)
HIGH(PRS=1)
VOP [6:0](programmed) {00 hex... 7F hex} Fig.23 VOP programming of ST7549T
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H[1:0]=[1:0] Partial screen mode A0 WR(R/W) 0 0 Flag D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 PS
Description Full display mode or partial screen mode selection PS PS=0:Full display mode with MUX 1:68 PS=1:Partial screen mode with MUX 1:17 or MUX 1:33 When enter Partial screen mode , COMS also works. The DDRAM position of COMS is at page9(D0) Partial screen size This instruction can select partial screen size A0 WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 0 0 WS Description WS=0:partail screen mode with MUX 1:17(16 Common + COMS) WS WS=1:Partial screen mode with MUX 1:33( 32 Common + COMS) Display part This instruction can select partial screen modes A0 WR(R/W) D7 D6 D5 D4 D3 D2 0 0 0 0 0 1 0 DP2 Flag Status Flag
D1 DP1
D0 DP0
Description Display common DDRAM position 0 0 0 Start from common 0 Start from page 0 0 0 1 Start from common 8 Start from page 1 0 1 0 Start from common 16 Start from page 2 0 1 1 Start from common 24 Start from page 3 DP2 DP1 DP0 1 0 0 Start from common 32 Start from page 4 1 0 1 Start from common 40 Start from page 5 1 1 0 Start from common 48 Start from page 6 1 1 1 Start from common 56 Start from page 7 The range of display common and DDRAM depends on the "WS" register . For example , if WS=1 and DP[2:0]=001 ,then display common is common 8 to common 39 and DDRAM position is page 1 to page4 and COMS is at page 9 . Moreover the bottom of DP[2:0] is common 66, when the range is over common66,there will be no more common output to display H[1:0]=[1:1] Reset This instruction resets initial display line, column address, page address, and common output status select to their initial status .This instruction cannot initialize the LCD power supply, which is initialized by the RESB pin. A0 D7 D6 D5 D4 D3 D2 D1 D0 WR(R/W) 0 0 0 0 0 0 0 0 1 1 Frame frequency A0 D7 D6 D5 D4 D3 D2 D1 D0 WR(R/W) 0 0 0 0 0 0 1 FR2 FR1 FR0 This command is used to set the frame frequency. FR2 FR1 FR0 FR frequency 0 0 0 55 Hz 15% 0 0 1 65 Hz 15% 0 1 0 68 Hz 15% 0 1 1 70 Hz 15% 1 0 0 73 Hz 10% 1 0 1 76 Hz 15% 1 1 0 80 Hz 15% 1 1 1 137 Hz 15%
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Release N-line inversion ST7549T returns to the frame inversion condition from the N-line inversion condition. A0 D7 D6 D5 D4 D3 D2 D1 WR(R/W) 0 0 0 1 0 NL4 NL3 NL2 NL1 D0 NL0
Set N-line inversion Sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the phase of the internal LCD AC signal (M) Note: The N-line inversion mode will be disabled when partial display mode enter. After the partial display mode end, the N-line inversion mode will return as it was. NL4 0 0 0 0 : 1 1 1 NL3 0 0 0 0 : 1 1 1 NL2 0 0 0 0 : 1 1 1 NL1 0 0 1 1 : 0 1 1 NL0 0 1 0 1 : 1 0 1 Selected n-line inversion 0-line inversion (frame inversion) 3-line inversion 4-line inversion 5-line inversion : 31-line inversion 32-line inversion 33-line inversion
Booster Efficiency & Booster stages A0 D7 D6 D5 D4 D3 D2 D1 D0 WR(R/W) 0 0 1 0 0 1 BE1 BE0 PC1 PC0 Booster Efficiency The ST7549T incorporates software configurable Booster Efficiency. It could be used with Voltage multiplier to get the suitable VOUT and Power consumption .Using lower Booster Efficiency level will get the lower VOUT & lower Power consumption. Default setting is Level 2.(suggest level) Flag Description BE1 BE0 0 0 Booster Efficiency Level 4 BE[1:0] 0 1 Booster Efficiency Level 3 1 0 Booster Efficiency Level 2(default) 1 1 Booster Efficiency Level 1 Booster stages The ST7549T incorporates a software configurable voltage multiplier. After reset (RESB), the default voltage multiplier is related to "CP" pin(see page 11). Other voltage multiplier factors are set via this command . Flag Description PC1 PC0 0 0 2*voltage multiplier(Booster X2) PC1, PC0 0 1 3*voltage multiplier(Booster X3) 1 0 4*voltage multiplier(Booster X4) 1 1 5*voltage multiplier(Booster X5) Self Test/Identification Data Read( Only used under 3-LINE interface) These command set SDAOUT to Diver TxData-mode and enable to read the status of B1...B4 (ID1...ID4) from output of multiplexer inside the driver. A0 D7 D6 D5 D4 D3 D2 D1 D0 Description 0 1 1 0 1 1 0 1 0 Read the status of the B1 (ID1) 0 1 1 0 1 1 0 1 1 Read the status of the B2 (ID2) 0 1 1 0 1 1 1 0 0 Read the status of the B3 (ID3) 0 1 1 0 1 1 1 0 1 Read the status of the B4 (ID4)
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10. COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
User System Setup by External Pins
Start of Initialization
Power ON(VDD-VSS) Keeping the /RESB Pin="L"
Waiting for Stabilizing the Power
Release the reset state. (/RESB pin="H") Waiting reset circuit stablized(>1ms)
Function set PD=0,H1=0,H0=1 SET Bias system SET DO SET VOP Function set PD=0 ,H1=0, H0=0 Set VLCD Range(PRS) Display control D=1 E=0 (Normal) Set X , Y address
End of Initialization
Fig.24 Initializing with the Built-in Power Supply Circuits
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11. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2. Parameter Power Supply Voltage Power supply voltage Power supply voltage (VDD standard) Power supply voltage (VDD standard) Input voltage Operating temperature Storage temperature VDD1 VDD2 VOUTOUT, VOUTIN , V0 V1, V2, V3, V4 CSB,RESB,A0,/WR,/RD,D7~D0 TOPR TSTR Symbol Conditions -0.3 ~ 3.6 -0.3 ~ 3.6 -0.3~13.5 0.3 to VOUTIN -0.5 ~ 5 -30 to +85 -65 to +150 V V V V V C C Unit
Notes 1. Stresses over those listed in Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VOUTIN V0 V1 V2 V3 V4 VSS
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12. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
13. DC CHARACTERISTICS
VDD1 = 1.7 V to 3.3V; VSS = 0 V; Tamb = -30 to +85; unless otherwise specified. Rating Item Symbol Condition Min. Typ. Operating Voltage (1) VDD1 1.7 -- Max. 3.3 Units V Applicable Pin VDD1
Operating Voltage (2) High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current
VDD2 VIHC VILC VOHC VOLC ILI ILO
(Relative to VSS)
2.4 0.7 x VDD VSS
-- -- -- -- -- -- -- 2.0 3.2
3.3 VDD 0.3 x VDD VDD 0.3 x VDD 1.0 3.0 --
V V V V V A A
VDD2
IOUT=-500uA; VDD=1.7V IOUT=500uA; VDD=1.7V
0.7 x VDD VSS -1.0 -3.0
Liquid Crystal Resistance
Driver
ON
RON
Ta = 25C (Relative to VSS)
VOUTIN = 13.0 V VOUTIN = 8.0 V
-- --
K --
SEGn COMn *6
Frame frequency
FR
65.7
73
80.3
Hz
Item Internal Power Input voltage
Symbol VDD1
Condition (Relative To VSS) (Relative To VSS) (Relative To VSS)
Min. 1.7 4.5 4.5
Rating Typ. -- -- --
Max. 3.3 13.5 13.5
Units V V V
Applicable Pin
Supply Step-up output VOUTOUT voltage Circuit Voltage regulator Circuit Operating VOUTIN Voltage
VOUTOUT VOUTIN
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Dynamic Consumption Current : During Display, with the Internal Power Supply ON Current consumed by total ICs(bare die) Rating Test pattern Symbol Condition Units Notes Min. Typ. Max. VDD = 3.0 V, Display Pattern Booster X4 ISS -- 300 400 A SNOW V0 - VSS = 9.0 V Bias=1/9 Power Down Display Pattern SNOW (Continues) ISS Ta = 25C VDD = 3.0 V, Booster X4 V0 - VSS = 9.0 V Bias=1/9 Data write frequncy: 1M Hz -- 0.01 2 A
ISS
--
350
450
A
Notes to the DC characteristics 1. The maximum possible VOUT voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock 3. Power-down mode. During power down all static currents are switched off. 4. If external VOUTIN, the display load current is not transmitted to IDD. 5. VOUT external voltage applied to VOUTIN pin; VOUTIN disconnected from VOUTOUT (no connect)
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14. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
/CSB tCYC8 tCCLR,tCCLW WR,RD tCCHR,tCCHW tDS8 D0 to D7 (Write) tDH8
tACC8 D0 to D7 (Read)
tOH8
Figure 26. (VDD = 3.3V , Ta =-30~85C) Rating Units Min. Max. 10 100 400 80 80 140 80 80 10 CL = 100 pF CL = 100 pF -- 10 -- -- 70 50 -- -- -- -- -- -- ns
Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time
Signal
Symbol tAH8
Condition
A0
tAW8 tCYC8
WR
tCCLW tCCHW tCCLR tCCHR tDS8
RD
D0 to D7
tDH8 tACC8 tOH8
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Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition (VDD = 2.8V , Ta =-30~85C) Rating Units Min. Max. 15 150 600 220 180 220 180 120 15 -- 10 -- -- -- -- -- -- -- -- -- 140 100 ns
RD
Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time
Signal
Symbol tAH8
Condition
(VDD = 1.8V , Ta =-30~85C) Rating Units Min. Max. 30 200 1000 360 280 360 280 200 30 -- -- 240 200 -- -- -- -- -- -- ns
A0
tAW8 tCYC8
WR
tCCLW tCCHW tCCLR tCCHR tDS8
RD
D0 to D7
tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF
-- 10
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0 R/W tAW6 CSB tCYC6 tCCLR,tCCLW E tCCHR,tCCHW tDS6 D0 to D7 (Write) tDH6 tAH6
tACC6 D0 to D7 (Read)
tOH6
Figure 27. (VDD = 3.3V , Ta =-30~85C) Rating Units Min. Max. 10 80 240 80 80 80 140 80 10 CL = 100 pF CL = 100 pF -- 10 -- -- 70 50 -- -- -- -- -- -- ns
Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time
Signal
Symbol tAH6
Condition
A0
tAW6 tCYC6
WR
tEWLW tEWHW tEWLR tEWHR tDS6
RD
D0 to D7
tDH6 tACC6 tOH6
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Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time D0 to D7 WR A0 Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition (VDD = 2.8V , Ta =-30~85C) Rating Units Min. Max. 15 100 400 220 180 220 180 120 15 -- 10 -- -- -- -- -- -- -- -- -- 140 100 ns
RD
Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Address hold time READ access time READ Output disable time
Signal
Symbol tAH6
Condition
(VDD = 1.8V , Ta =-40~85C) Rating Units Min. Max. 30 150 640 360 280 360 280 200 30 -- -- -- -- -- -- -- -- -- 240 200 ns
A0
tAW6 tCYC6
WR
tEWLW tEWHW tEWLR tEWHR tDS6
RD
D0 to D7
tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF
-- 10
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CSB being "L" and E.
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SERIAL INTERFACE(4-Line Interface)
tCCSS tCSH
/CSB
tSAS A0 tSCYC tSLW SCLK
tSAH
tSHW tf tSDS SDA tr tSDH
Fig 28. Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SI CSB SCL A0 SI CSB SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Condition (VDD = 3.3V , Ta =-30~85C) Rating Units Min. Max. 150 75 75 20 100 20 10 20 -- -- -- -- -- -- -- -- ns
Signal
140 -- (VDD = 2.8V , Ta =-30~85C) Rating Units Min. Max. 300 -- 150 150 30 150 30 20 30 200 -- -- -- -- -- -- -- -- ns
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Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time A0 SI CSB SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS Condition (VDD=1.8V,Ta=-30~85) Rating Units Min. Max. 500 -- 250 250 60 250 60 50 40 350 -- -- -- -- -- -- -- -- ns
CS-SCL time tCSH *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
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SERIAL INTERFACE(3-Line Interface)
tCCSS /CS1 (CS2="1") tCSH
tSCYC tSLW SCL tSHW tf tSDS SI tr tSDH
Fig 28. (VDD=3.3V,Ta=-30~85) Rating Units Min. Max. 150 75 75 20 10 20 140 -- -- -- -- -- -- -- ns
Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time
Signal
Symbol tSCYC
Condition
SCL
tSHW tSLW tSDS tSDH tCSS tCSH
SI CSB
Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time
Signal
Symbol tSCYC
Condition
(VDD=2.8V,Ta=-30~85) Rating Units Min. Max. 300 -- 150 150 30 20 30 200 -- -- -- -- -- -- ns
SCL
tSHW tSLW tSDS tSDH tCSS tCSH
SI CSB
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Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH Condition (VDD=1.8V,Ta=-30~85) Rating Units Min. Max. 500 -- 250 250 60 50 40 350 -- -- -- -- -- -- ns
tCSS CSB CS-SCL time tCSH *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard. SERIAL INTERFACE(I C Interface)
2
SD A
tBUF tLOW tHIGH
SCL
tDH;STA tHD;DAT tSU;DAT
(VDD=3.3V,Ta=-30~85) Rating Units Min. Max. 400 kHZ 1.3 us 0.6 us 100 ns 0 0.9 us 20+0.1Cb 300 ns 20+0.1Cb 300 ns 400 pF 0.6 us 0.6 us 0.6 us 50 ns 1.3 us
Item SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time SCL,SDA rise time SCL,SDA fall time Capacitive load represented by each bus line Setup time for a repeated START condition Start condition hold time Setup time for STOP condition Tolerable spike width on bus BUS free time between a STOP and START condition
Signal Symbol SCL SCL SCL SI SI SCL SCL SI SI SCL FSCLK TLOW THIGH TSU;Data THD;Data TR TF Cb TSU;SUA THD;STA TSU;STO TSW TBUF
Condition
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15. RESET TIMING
tRW /RES
tR Internal status During reset Reset complete
Fig 29. Item Reset time Reset "L" pulse width Item Reset time Reset "L" pulse width Item Reset time Reset "L" pulse width Signal RESB Signal RESB Signal RESB Symbol tR tRW Symbol tR tRW Symbol tR tRW Condition Condition Condition (VDD = 3.3V , Ta = -30 to 85C ) Rating Units Min. Typ. Max. -- -- 1 us 1 -- -- us (VDD = 2.8V , Ta = -30 to 85C ) Rating Units Min. Typ. Max. -- -- 2.0 us 2.0 -- -- us (VDD = 1.8V , Ta = -30 to 85C ) Rating Units Min. Typ. Max. -- -- 3.0 us 3.0 -- -- us
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APPLICATION NOTE
ST7549T
Resolution : 68(67COM+ICON)*102(SEG) Interface : 6800 series Internal analog circuit Internal OSC Booster : X5 Bias ratio default : 1/9 (bias ratio can be changed by instruction) C=1.0 uF R=10 K
................ 123 COM8 113 114 115 SEG101 COMS COM0 ................ ............................................. 11 12 .............................................
OSC : Vdd T8 : Vdd T9 : Vdd T10 : Vdd T11 : Vss PS0 : Vss PS1 : Vdd PS2 : Vdd CP : Vdd BR : Vdd
.......................................... .......................................... 1
COM33 SEG0 COM44
COM43 230 ..................................... .....................................
COM9 ..................................... COM22 138 COM23 .....................................
124
ST7549T
137
150~153 194~197 198~199 200~201 164~167 183~186
COM57 147 193 192 191 190 189 188 187 208 207 206 205 204 203 202 216 149 148 163 162 161 160 159 158 157 156 155 154 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168
217
................ COM32 ................
....................... COM58
COM66 COMS V4 V3 V2 V1 V0 V LCDOUT V LCDIN Vss T5 T4 T3 T2 T1 T0 VRS Vss OSC D0 D1 D2 D3 D4 D5 D6 D7 Vdd1 A0 /RD /WR CSB RESB Vdd2 T11 T10 CP T9 T8 Vss BR PS2 PS1 PS0 Vdd1 T7 T6 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VOUT Vss D0 D1 D2 D3 D4 D5 D6 D7 A0 /RD /WR CSB RESB Vdd Vdd C=1.0uF R=10K C=1.0uF
.......................
IC PAD SIDE
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ST7549T
Resolution : 68(67COM+ICON)*102(SEG) Interface : 8080 series Internal analog circuit Internal OSC Booster : X5 Bias ratio default : 1/9 (bias ratio can be changed by instruction) C=1.0 uF
................ 123 COM8 113 114 115 SEG101 COMS COM0 ................ ............................................. 11 12 .............................................
OSC : Vdd T8 : Vdd T9 : Vdd T10 : Vdd T11 : Vss PS0 : Vss PS1 : Vdd PS2 : Vss CP : Vdd BR : Vdd
.......................................... .......................................... 1
COM33 SEG0 COM44
COM43 230 ..................................... .....................................
COM9 ..................................... COM22 138 COM23 .....................................
124
ST7549T
137
150~153 194~197 198~199 200~201 164~167 183~186
COM57 216 147 193 192 191 190 189 188 187 208 207 206 205 204 203 202 149 148 163 162 161 160 159 158 157 156 155 154 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168
217
................ COM32 ................
....................... COM66 COMS V4 V3 V2 V1 V0 V LCDOUT V LCDIN Vss T5 T4 T3 T2 T1 T0 VRS Vss OSC D0 D1 D2 D3 D4 D5 D6 D7 Vdd1 A0 /RD /WR CSB RESB Vdd2 T11 T10 CP T9 T8 Vss BR PS2 PS1 PS0 Vdd1 T7 T6 ....................... 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VOUT Vss D0 D1 D2 D3 D4 D5 D6 D7 A0 /RD /WR CSB RESB Vdd Vdd C=1.0uF R=10K C=1.0uF COM58
IC PAD SIDE
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ST7549T
Resolution : 68(67COM+ICON)*102(SEG) Interface : 4-line Internal analog circuit Internal OSC Booster : X5 Bias ratio default : 1/9 (bias ratio can be changed by instruction) C=1.0 uF R=10 K
................ 123 COM8 113 114 115 SEG101 COMS COM0 ................ ............................................. 11 12 .............................................
OSC : Vdd T8 : Vdd T9 : Vdd T10 : Vdd T11 : Vss PS0 : Vss PS1 : Vss PS2 : Vss CP : Vdd BR : Vdd
.......................................... .......................................... 1
COM33 SEG0 COM44
COM43 230 ..................................... .....................................
COM9 ..................................... COM22 138 COM23 .....................................
124
ST7549T
137
150~153 194~197 198~199 200~201 164~167 183~186
COM57 216 147 193 192 191 190 189 188 187 208 207 206 205 204 203 202 149 148 163 162 161 160 159 158 157 156 155 154 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168
217
................ COM32 ................
....................... COM58
COM66 COMS V4 V3 V2 V1 V0 V LCDOUT V LCDIN Vss T5 T4 T3 T2 T1 T0 VRS Vss OSC
(SCLK)D0 (SDA)D1 (SDA)D2
(SDA)D3 D4 D5 D6 D7
Vdd1 A0 /RD /WR CSB RESB Vdd2 T11 T10 CP T9 T8 Vss BR PS2 PS1 PS0 Vdd1 T7 T6 Vdd C=1.0uF R=10K
.......................
IC PAD SIDE
8 7 6 5 4 3 2 1 VOUT Vss SCLK SDA A0 CSB RESB Vdd C=1.0uF
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ST7549T
Resolution : 68(67COM+ICON)*102(SEG) Interface : 3-line Internal analog circuit Internal OSC Booster : X5 Bias ratio default : 1/9 (bias ratio can be changed by instruction) C=1.0 uF R=10 K
................ 123 COM8 113 114 115 SEG101 COMS COM0 ................ .............................................
OSC : Vdd T8 : Vdd T9 : Vdd T10 : Vdd T11 : Vss PS0 : Vss PS1 : Vss PS2 : Vdd CP : Vdd BR : Vdd (ID1,ID2,ID3,ID4)=(1,1,1,1)
.......................................... 11 12 .......................................... 1
.............................................
COM33 SEG0 COM44
COM43 230 ..................................... .....................................
COM9 ..................................... COM22 138 COM23 .....................................
124
ST7549T
137
150~153 194~197 198~199 200~201 164~167 183~186
COM57 216 147 149 148 163 162 161 160 159 158 157 156 155 154 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 193 192 191 190 189 188 187 208 207 206 205 204 203 202
217
................ COM32 ................
....................... COM58
(SDA_OUT)D3
(SDA_OUT)D2
COM66 COMS V4 V3 V2 V1 V0 V LCDOUT V LCDIN Vss T5 T4 T3 T2 T1 T0 VRS Vss OSC
(SCLK)D0
(SDA_IN)D1
Vdd1 A0 /RD /WR CSB RESB Vdd2 T11 T10 CP T9 T8 Vss BR PS2 PS1 PS0 Vdd1 T7 T6 Vdd C=1.0uF R=10K
D7(ID4)
D6(ID3)
D5(ID2)
D4(ID1)
.......................
IC PAD SIDE
7 6 5 4 3 2 1 VOUT Vss SCLK SDA CSB RESB Vdd C=1.0uF
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ST7549T
Resolution : 68(67COM+ICON)*102(SEG) Interface : I2C Internal analog circuit Internal OSC Booster : X5 Bias ratio default : 1/9 (bias ratio can be changed by instruction) SA[1:0]:=(0,0) (SA[1:0] are slave address of I2C) C=1.0 uF R=10 K
................ 123 COM8 113 114 115 SEG101 COMS COM0 ................ ............................................. 11 12 .............................................
OSC : Vdd T8 : Vdd T9 : Vdd T10 : Vdd T11 : Vss PS0 : Vdd PS1 : Vdd PS2 : Vdd CP : Vdd BR : Vdd
.......................................... .......................................... 1
COM33 SEG0 COM44
COM43 230 ..................................... .....................................
COM9 ..................................... COM22 138 COM23 .....................................
124
ST7549T
137
150~153 194~197 198~199 200~201 164~167 183~186
COM57 216 147 149 148 163 162 161 160 159 158 157 156 155 154 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 193 192 191 190 189 188 187 208 207 206 205 204 203 202
217
................ COM32 ................
....................... COM58
COM66 COMS V4 V3 V2 V1 V0 V LCDOUT V LCDIN Vss T5 T4 T3 T2 T1 T0 VRS Vss OSC
(SDA_OUT)D3
(X)D4 (X)D5 (SA1)D6 (SA0)D7 Vdd1 A0 /RD /WR CSB RESB Vdd2 T11 T10 CP T9 T8 Vss BR PS2 PS1 PS0 Vdd1 T7 T6 6 5 4 3 2 1 VOUT Vss SCLK SDA RESB Vdd Vdd R=10K C=1.0uF C=1.0uF
(SCLK)D0
(SDA_OUT)D2
(SDA_IN)D1
.......................
IC PAD SIDE
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History
Version 1.1 1.2 1.3 History Change the IC thickness to 480um from version 1.1 l l l l Modify function description Modify VLCD, V0, VOP, VOUT Update Part Number to ST7459T-G2 (for thickness 480 um) Add Frame Rate range. 2005/12/06 Date 2005/11/28 2005/11/30
Ver 1.3
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